This invention relates to a semiconductor memory device.
Semiconductor memory devices are used indispensably as the main memories of modern computer systems. In general, a semiconductor memory device is comprised of a plurality of memory cells matrix arrayed on a semiconductor chip, as well as of row and column decoders for decoding row and column address signals. The row decoder is connected to word lines laid along rows of a memory cell matrix so that memory cells arrayed in the same row can be selected by the row decoder through the associated word line. Similarly, bit lines are laid along columns of the matrix array. The memory cells in the same column can be selected by the column decoder through the associated bit line.
The dynamic RAMs have been used predominantly for recent high density semiconductor memory devices. The memory cell of the dynamic RAM has a relatively simple structure in that its essential elements are, for example, a capacitor and a transfer gate. The current path of the transfer gate is connected between the capacitor and the bit line. A conduction state of the transfer gate is controlled by the row decoder through the associated word line. The memory cell stores binary data "0" or "1" according to a charge amount of the capacitor. Charge in the capacitor tends to decrease with time due to a leakage current in the semiconductor chip. In the case of the dynamic RAM, therefore, the memory cells must be refreshed to maintain their validity before data in the capacitor volatilizes due to a current leak. As a means of refreshing a memory cell, data in the memory cell is read out and the same data as that read out is rewritten into the same memory cell. To be more specific, a bit line is precharged up to a predetermined potential, e.g., 5 V. Then, the transfer gate is turned on, and the potential of the bit line is varied according to the charge amount of the capacitor. A potential variation of the bit line is sensed, as the contents of the memory cell, by, for example, a sense amplifier. The sense amplifier sets the bit line potential to 0 V or 5 V according to the sensed data, and either charges or discharges the capacitor. Then, the transfer gate is turned off so that a predetermined amount of charge is held in the capacitor. In the dynamic RAM of 256 K bits, for example, because the capacitors are discretely manufactured and minute in size, each capacitor cannot store a large amount of charge. Conventionally, all of the memory cells of the dynamic RAM are cyclically refreshed at periods of 4 ms or less. If the refresh cycle has a period of more than 4 ms, there is a great possibility that the data in the memory cells may be altered to become erroneous data.
Usually, in the dynamic RAMs, the refresh operation and the normal operation (i.e., read/write operation) are assigned to independent time bands, so that the memory cells can be periodically refreshed exclusive of other functions. In the refresh mode, the bit lines are used solely for refreshing the memory cells. For this reason, these bit lines cannot be used for the read/write operation. To avoid an erroneous operation, access to the dynamic RAM is prohibited during the refresh operation, this being one of the major negative factors serving to reduce the effective access speed of the dynamic RAM. Moreover, in designing a dynamic RAM, a designer must allow for the refresh timings of the dynamic RAM, a consideration which places an undue mental load upon the designer.
As for the layout and the connection of the components, the word lines are laid in the row direction of the memory cell matrix array, while the row decoder has multi-input logic gates which are directed in the column direction and disposed adjacent the ends of the word lines. The multi-input logic gates are connected for reception to row and refresh address signals through a plurality of address lines which are extended along the multi-input logic gates. The address input lines have a relatively large stray capacitance of, for example, 10 pF. Because of this large stray capacitance, it takes approximately 5 ns before the address line is set to a predetermined potential after the update of the address signal. Additionally, about 6 ns is taken for decoding the received address signal, since the multi-input logic gate is a combination of a plurality of NAND gates. How to reduce such a time delay associated with the decoding operation, for the purpose of improving the operation speed of the memory device, is a most significant problem in this field.